verilog - What is `+:` and `-:`? -

i've saw operator in verilog/systemverilog code.

logic [15:0] down_vect; logic [0:15] up_vect;  down_vect[lsb_base_expr +: width_expr] up_vect  [msb_base_expr +: width_expr] down_vect[msb_base_expr -: width_expr] up_vect  [lsb_base_expr -: width_expr] 

i've seen so, i'd ask this, when , how use it?

that particular syntax called indexed part select. it's useful when need select fixed number of bits variable offset within multi-bit register.

here's example of syntax:

reg [31:0] dword; reg [7:0] byte0; reg [7:0] byte1; reg [7:0] byte2; reg [7:0] byte3;  assign byte0 = dword[0 +: 8];    // same dword[7:0] assign byte1 = dword[8 +: 8];    // same dword[15:8] assign byte2 = dword[16 +: 8];   // same dword[23:16] assign byte3 = dword[24 +: 8];   // same dword[31:24] 

the biggest advantage syntax can use variable index. normal part selects in verilog require constants. attempting above dword[i+7:i] not allowed.

so if want select particular byte using variable select, can use indexed part select.

example using variable:

reg [31:0] dword; reg [7:0] byte;  reg [1:0] i;  // illegal due variable i, though width 8 bits assign byte = dword[(i*8)+7 : i*8];  // ** not allowed!  // use indexed part select  assign byte = dword[i*8 +: 8];