verilog - Running timing simulation in modelsim -

i've created small design in verilog , want run timing simulation. since know how vhdl files, figured i'll (almost) same way. unfortunately, it's not easy.

i've compiled design , received .sdo , .vho files. when i'm trying run testbench, receive error:

> vsim work.sdesign_tb # vsim work.sdesign_tb # loading work.sdesign_tb # altera version supports single hdl # ** fatal: (vsim-3039) c:/users/k_impl/sdesign_tb.v(17): instantiation of 'sdesign' failed. #    time: 0 ps  iteration: 0  instance: /sdesign_tb file: c:/users/k_impl/sdesign_tb.v # fatal error while loading design # error loading design 

it looks quartus 12.1 created vhdl files, while want simulate verilog design (and quartus supports 1 vhdl @ same time). i've tried way, adding .sdo files sdf , run simulation through "start simulation". showed error (almost same above). how can bypass it? or maybe there way of running timing simulation verilog designs?

to run timing simulation may need add altera_ver , device libraries.